riscvisel.h

// This file if part of the llir-opt project.
// Licensing information can be found in the LICENSE file.
// (C) 2018 Nandor Licker. All rights reserved.
 
#pragma once
 
#include <set>
#include <unordered_map>
 
#include <llvm/ADT/DenseMap.h>
#include <llvm/Analysis/OptimizationRemarkEmitter.h>
#include <llvm/CodeGen/MachineBasicBlock.h>
#include <llvm/IR/Module.h>
#include <llvm/IR/Type.h>
#include <llvm/Pass.h>
#include <llvm/Target/RISCV/RISCVInstrInfo.h>
#include <llvm/Target/RISCV/RISCVISelDAGToDAG.h>
#include <llvm/Target/RISCV/RISCVMachineFunctionInfo.h>
#include <llvm/Target/RISCV/RISCVRegisterInfo.h>
#include <llvm/Target/RISCV/RISCVSubtarget.h>
#include <llvm/Target/RISCV/RISCVTargetMachine.h>
 
#include "core/insts.h"
#include "emitter/isel.h"
#include "emitter/riscv/riscvcall.h"
 
class Data;
class Func;
class Inst;
class Prog;
 
 
 
class RISCVMatcher : public llvm::RISCVDAGMatcher {
public:
  RISCVMatcher(
      llvm::RISCVTargetMachine &tm,
      llvm::CodeGenOpt::Level ol,
      llvm::MachineFunction &mf
  );
  ~RISCVMatcher();
 
  llvm::SelectionDAG &GetDAG() const { return *CurDAG; }
  const llvm::TargetLowering *getTargetLowering() const override
  {
    return CurDAG->getMachineFunction().getSubtarget().getTargetLowering();
  }
 
private:
  llvm::RISCVTargetMachine &tm_;
};
 
 
 
class RISCVISel final : public ISel {
public:
  static char ID;
 
  RISCVISel(
      const Target &target,
      llvm::RISCVTargetMachine &tm,
      llvm::TargetLibraryInfo &libInfo,
      const Prog &prog,
      llvm::CodeGenOpt::Level ol,
      bool shared
  );
 
private:
  void Lower(llvm::MachineFunction &mf) override
  {
    m_.reset(new RISCVMatcher(tm_, ol_, mf));
  }
 
  SDValue GetRegArch(Register reg) override;
 
  void LowerArch(const Inst *inst) override;
 
  void LowerSyscall(const SyscallInst *inst) override;
  void LowerClone(const CloneInst *inst) override;
  void LowerReturn(const ReturnInst *inst) override;
  void LowerRaise(const RaiseInst *inst) override;
  void LowerSpawn(const SpawnInst *inst) override;
  void LowerLandingPad(const LandingPadInst *inst) override;
  void LowerSet(const SetInst *inst) override;
  void LowerXchg(const RISCV_XchgInst *inst);
  void LowerCmpXchg(const RISCV_CmpXchgInst *inst);
  void LowerFence(const RISCV_FenceInst *inst);
  void LowerGP(const RISCV_GpInst *inst);
 
  void LowerArguments(bool hasVAStart) override;
  void LowerVASetup(const RISCVCall &ci);
 
private:
  llvm::SelectionDAG &GetDAG() const override { return m_->GetDAG(); }
  void PreprocessISelDAG() override { m_->PreprocessISelDAG(); }
  void PostprocessISelDAG() override { m_->PostprocessISelDAG(); }
  void Select(SDNode *node) override { m_->Select(node); }
 
  llvm::Register GetStackRegister() const override { return llvm::RISCV::X2; }
 
private:
  void SaveVarArgRegisters(const RISCVCall &ci, bool isWin64);
  llvm::SDValue LowerCallee(ConstRef<Inst> inst);
  void LowerCallSite(llvm::SDValue chain, const CallSite *call) override;
 
private:
  llvm::RISCVTargetMachine &tm_;
  std::unique_ptr<RISCVMatcher> m_;
  llvm::Function *trampoline_;
  bool shared_;
};